1. Field of the Invention
The present invention relates to a receiving apparatus and a time correction method for the receiving apparatus. More particularly, the present invention is concerned with a receiving apparatus that corrects a time indicated by a clock unit by utilizing a synchronizing packet sent from a transmitting apparatus over an asynchronous network.
2. Description of the Related Art
In the past, a receiving apparatus including a clock unit which outputs time information has been known to correct a time indicated by the clock unit by utilizing a synchronizing packet sent from a transmitting apparatus over an asynchronous network.
FIG. 17 shows an example of the configuration of a receiving apparatus 400 in accordance with a related art. In FIG. 17, a portion of the receiving apparatus relating to time synchronization described in JP-A-2004-304809 is schematically shown. In the receiving apparatus 400, a synchronizing (hereinafter, sync) packet containing transmission time information is received from a transmitting apparatus over a local area network (LAN). A value indicated by a clock unit (counter) is rewritten with a time (counter value) represented by the transmission time information. Thus, the time indicated in the receiving apparatus is controlled to synchronize with the time indicated in the transmitting apparatus.
The receiving apparatus 400 includes a network interface 401, a sync packet receiving unit 402, a receiving time recording unit 403, and a time information recording unit 404. The receiving apparatus 400 further includes a magnitude-of-jitter calculation unit 405, an error calculation and digital-to-analog conversion (DAC) unit 406, and a clock generation unit 407, a clock unit 409, and a counter 408.
The clock unit 409 outputs time information. The clock unit 409 includes a counter that counts up responsively to a clock CLK generated by the clock generation unit 407. The counter 408 is a counter similar to the counter included in the clock unit 409, and counts up responsively to the clock CLK generated by the clock generation unit 407.
The sync packet receiving unit 402 receives a sync packet sent from a transmitting apparatus, which is not shown, via the network interface 401 over a LAN that is an asynchronous network. FIG. 18 shows an example of the structure of the sync packet. The sync packet includes an Ethernet frame header, an IP datagram header, a user datagram protocol (UDP) header, time stamp data, miscellaneous data items, and a cyclic redundancy check (CRC) character (a code for use in checking an error). The time stamp data is information representing the transmitting time of the sync packet.
The receiving time recording unit 403 records a counter value of the counter 408, which is obtained at a time point at which a sync packet is received by the sync packet receiving unit 402, as a receiving time. The time information recording unit 404 records a transmitting time represented by the time stamp data contained in the sync packet received by the sync packet receiving unit 402.
The magnitude-of-jitter calculation unit 405 calculates a magnitude of a jitter on the basis of the receiving times and transmitting times of two adjoining sync packets received by the sync packet receiving unit 402. In other words, the magnitude-of-jitter calculation unit 405 calculates as the magnitude of a jitter a difference between a first difference that is the difference between the receiving times and a second difference that is the difference between the transmitting times.
Now, assume that t(1), t(2), etc. denote receiving times and s(1), s(2), etc. denote transmitting times. Herein, the numeral in parentheses denotes a sample number assigned to a sync packet. For example, t(a) and s(a) shall denote the receiving time and transmitting time respectively of a certain sync packet, and t(b) and s(b) shall denote the receiving time and transmitting time respectively of a subsequent sync packet. In this case, the magnitude-of-jitter calculation unit 405 calculates a magnitude of a jitter according to an equation (1) presented below.Magnitude of a jitter=t(b)−t(a)−(s(b)−s(a))  (1)
After performing appropriate filtering processing on magnitudes of jitters calculated by the magnitude-of-jitter calculation unit 405, the error calculation and DAC unit 406 performs quantization, conversion into analog values, and low-pass filtering processing in that order so as to produce an error voltage VC. The error calculation and DAC unit 406 feeds the error voltage VC to the clock generation unit 407 as a control voltage for a clock frequency.
The clock generation unit 407 generates, as mentioned above, a clock CLK that is fed to the clock unit 409 and counter 408. The clock generation unit 407 is formed using, for example, a voltage-controlled crystal oscillator (VCXO).
Time synchronizing actions to be performed in the receiving apparatus 400 shown in FIG. 17 will be described below.
When a sync packet (see FIG. 18) sent from a transmitting apparatus via the network interface 401 over a LAN is received by the sync packet receiving unit 402, the counter value of the counter 408 is recorded as a receiving time in the receiving time recording unit 403. At this time, in the time information recording unit 404, a transmitting time represented by time stamp data contained in the received sync packet is recorded.
In the magnitude-of-jitter calculation unit 405, the receiving times recorded in the receiving time recording unit 403 and the transmitting times recorded in the time information recording unit 404 are used to calculate magnitudes of jitters according to the equation (1) to which the receiving times of two adjoining sync packets and the transmitting times thereof are assigned. Under a situation under which time synchronization is unsusceptible to a variation in a delay time of a sync packet occurring over the network, the magnitude of a jitter corresponds to an error in a clock frequency between transmitting and receiving sides. Under a situation under which time synchronization is susceptible to the variation in the delay time of a sync packet occurring over the network, the magnitude of a jitter corresponds to the combination of the error in the clock frequency between the transmitting and receiving sides, and the variation in the delay time.
The magnitudes of jitters calculated by the magnitude-of-jitter calculation unit 405 are fed to the error calculation and DAC unit 406. In the error calculation and DAC unit 406, after the magnitudes of jitters are subjected to appropriate filtering processing, quantization, conversion into analog values, and low-pass filtering processing are carried out in that order. Eventually, an error voltage VC is produced. The error voltage VC is fed to the clock generation unit 407, and used to control the frequency of the clock CLK to be generated by the clock generation unit 407. The counter 408, receiving time recording unit 403, magnitude-of-jitter calculation unit 405, error calculation and DAC unit 406, and clock generation unit 407 constitute a frequency-locked loop.
As mentioned above, when the frequency of the clock CLK generated by the clock generation unit 407 is controlled by the frequency-locked loop, the time (counter value) indicated by the clock unit 409 is corrected. Specifically, when a sync packet is received by the sync packet receiving unit 402, the time (counter value) of the clock unit 409 is rewritten with a transmitting time (counter value) represented by time stamp data contained in the sync packet. Thus, the time (counter value) of the clock unit 409 is controlled to synchronize with the time (counter value) indicated by a clock unit included in a transmitting apparatus that is not shown. Information on the time (counter value) of the clock unit 409 is fed to, for example, a sync signal generation unit that is not shown, and used to phase the sync signals employed in the receiving apparatus and transmitting apparatus respectively.